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neurologyYou need to know

• The Arithmetic and Logic Unit performs arithmetic calculations, Boolean logic operations, comparisons and bit shifts, while the Control Unit coordinates the fetch-decode-execute cycle by sending control signals.
• The Program Counter stores the address of the next instruction, the Memory Address Register stores the address currently being accessed, and the Memory Data Register stores data or an instruction being transferred to or from memory.
• The Current Instruction Register stores the instruction currently being decoded or executed, while the Accumulator stores intermediate results produced by the Arithmetic and Logic Unit.
• The address bus carries memory addresses from the processor, the data bus carries data and instructions between components, and the control bus carries signals such as read, write and clock signals.
• Assembly-language instructions correspond closely to processor operations: the opcode identifies the operation and the operand identifies data, a register or an address on which the operation acts.
• During fetch, the Program Counter value is copied to the Memory Address Register, the addressed instruction is copied through the Memory Data Register to the Current Instruction Register, and the Program Counter is incremented.
• During decode, the Control Unit interprets the instruction's opcode and operand; during execute, it sends control signals so that the required operation is performed and any result is stored.
• Clock speed is the number of processor cycles completed per second, but processor performance also depends on architecture, instruction type, cache, core count and the software being executed.
• Processor cache is small, fast memory close to or inside the CPU that stores frequently or recently used instructions and data, reducing the time spent accessing RAM.
• Multiple processor cores can execute more than one instruction stream at once, but performance improves only when an operating system and application can divide work into tasks that run concurrently.
• Pipelining improves throughput by overlapping the fetch, decode and execute stages of different instructions, although branches and data dependencies can cause the pipeline to stall or be flushed.
• Von Neumann architecture stores instructions and data in the same memory and transfers them along shared buses, creating a potential bottleneck because instructions and data compete for access.
• Harvard architecture uses separate memories and buses for instructions and data, allowing both to be accessed simultaneously, while many contemporary processors use a modified Harvard design with shared main memory but separate instruction and data caches.
• CISC processors provide many specialised, often variable-length instructions that may take several clock cycles, whereas RISC processors use a smaller set of simpler, often fixed-length instructions designed for rapid execution and efficient pipelining.
• Graphics Processing Units contain many smaller processing units that perform similar calculations in parallel, making them useful for graphics rendering, machine learning, simulations, cryptocurrency calculations and large-scale data processing.
• Parallel processing divides a problem into tasks that are executed simultaneously by multiple cores or processors, but it is less effective when tasks must be completed sequentially or require frequent communication.
• Input devices capture data for a computer system, output devices communicate processed information, and suitable devices are selected according to factors such as data type, accuracy, speed, environment, accessibility and cost.
• Magnetic storage offers high capacity at low cost but contains moving parts; flash storage has no moving parts and is portable and durable but has limited write cycles; optical storage uses laser-readable discs and is useful for distribution or archiving but has lower capacity and speed.
• RAM is volatile, writable memory that stores programs and data currently in use, whereas ROM is non-volatile memory that stores instructions or data that should persist when power is removed, such as firmware.
• Virtual storage stores files on remote networked servers managed by a provider, enabling access, synchronisation and sharing across devices but requiring network access and creating security, privacy and provider-dependence risks.

• Trace the fetch-decode-execute cycle by recording the correct changes to the Program Counter, Memory Address Register, Memory Data Register, Current Instruction Register and Accumulator at each stage.
• Interpret simple assembly-language instructions by identifying the opcode and operand and explaining how data, address and control buses support their execution.
• Compare Von Neumann, Harvard and contemporary processor architectures in terms of memory organisation, buses, simultaneous access and performance.
• Evaluate how clock speed, cache size and core count affect CPU performance, recognising that the effect depends on processor architecture and whether software supports parallel execution.
• Explain how pipelining increases instruction throughput and identify situations, such as branch instructions and data dependencies, that can reduce its benefit.
• Compare CISC and RISC processors using instruction-set size, instruction complexity, instruction length, execution cycles, memory use and suitability for pipelining.
• Determine whether a task is suitable for multicore, GPU or parallel processing by assessing whether it can be divided into independent calculations.
• Select appropriate input, output and storage devices for a stated problem and justify the choice using capacity, speed, portability, durability, reliability, accuracy, cost and operating environment.
• Compare magnetic, flash, optical and virtual storage for a given scenario, including their capacity, speed, durability, portability, connectivity and security implications.